1. Field of the Invention
The invention relates to audio devices, and in particular, to anti-glitch devices in audio DACs.
2. Description of the Related Art
FIG. 1 shows a conventional Delta-Sigma DAC for converting a 16-bit digital signal to an audible signal Vout. The Delta-Sigma technique is popular because it achieves high resolution and quality with effective hardware implementations. An interpolator 102 receives an n-bit digital signal at a first sampling rate, and performs an interpolation to generate an n-bit output signal at a second, higher sampling rate. A Delta-Sigma modulator 104 receives the output signal from the interpolator 102 and shapes the quantization noises therein, thereby generating a shaped signal as a substantially linear analog representation of the 16-bit digital signal within a pass band. A DAC 106 then converts the shaped signal to an analog form, and a filter 110 filters high frequency noises therein to output the audible signal Vout.
When powering up, a system clock (not shown) requires a period of transient time to settle, and the Delta-Sigma modulator 104 also takes time to converge to stability. Random digital signals may be generated during the period, and amplified by the DAC 106 to output glitch noise. In the filter 110, an inverter 120 is conventionally implemented to avoid power-up glitches. A logic high signal is input to the inverter 120 when powering up, thus the inverter 120 enters a high impedance (High-Z) mode that forms an equivalent open circuit for the output node A. In this way, the power-up glitches are not passed to the output of filter 110. When the Delta-Sigma modulator 104 completes initialization, a zero pattern is output, and the inverter 120 returns to normal mode from the High-Z mode, passing the zero pattern to the filter 110. The zero pattern does not generate audible sounds through the filter 110. Additionally, a reference voltage Vref for the operational amplifier OP1 is coupled to ground by a switch 112 according to the control signal #ctrl when powering up, and the filter 110 forms a unity gain buffer that is also capable of avoiding power-up glitches. The reference voltage Vref is typically cascaded to a large capacitor (not shown) to obtain higher SNR. When the inverter 120 returns from High-Z mode to normal mode, the control signal #ctrl simultaneously switches to a logic low, such that the reference voltage Vref gradually increases to its operating point according to the RC constant.
In FIG. 1, an alternative implementation provides an output switch 114 coupled to the output of the operational amplifier OP1. The output switch 114 as well as the switch 112, may be a NMOS. When powering up, a control signal #ctrl of logic high is sent to the output switch 114, coupling the audible signal Vout to ground. The power-up glitches output from the operational amplifier OP1 are thus instantly avoided.
The High-Z mode solution, however, cannot be applied to finite impulse response (FIR) based Delta-Sigma DACs or switched capacitor architectures. Additionally, the zero patterns generated from the Delta-Sigma modulator 104 may still render glitches since the duty cycle transient of the zero pattern is unpredictable for the filter 110. The output switch 114 may not effectively pull the audible signal Vout to ground because the operational amplifier OP1 may output a significantly large loading. An improved anti-glitch circuit is therefore desirable.